1. Field of the Invention
The present invention relates to an information processing apparatus which delivers an access instruction to an external memory and, in particular, an information processing apparatus having the function of, for example, saving and restoring, at high speed, data elements showing the inner state of a processor's register file and status word upon an interrupt response, upon a subroutine call and upon a return, etc.
2. Description of the Related Art
Generally in the information processing apparatus using a microprocessor, in order that, upon the occurrence of an interrupt, a corresponding interrupt processing may be performed by switching the processor's run state, it is necessary to, upon the occurrence of such an interrupt, temporarily reserve the inner state of the processor's register, as well as the inner states, such as status words, condition code and mode bits. For this reason, the inner state of the register, etc. is continuously saved in an external stack or in a memory at a specifically reserved address. At the completion of such an interrupt, the saved data is continuously read from the corresponding memory address so that the register's inner state is restored.
In the saving and restoring steps made in a continuous access mode, an increase in the number of registers results in a longer time spent for continuous access. Consequently, there is a disadvantage of involving an increase of an interrupt overhead, including an interrupt entering time and returning time due to a slow interrupt response.
In order to enhance a processing efficiency using a high level language, the microprocessor has been equipped with 8 to 16 registers of 16 to 32-bit capacity, involving an increase of an interrupt overhead resulting from the data saving to a register and restoring to an original location.
In order to solve the aforementioned problem, the so-called "register bank switching system" has been adopted in which two or more sets of registers are provided in a microprocessor and, upon the occurrence of an interrupt, an involved register set is switched to another register set. This system is disclosed, for example, in "Electronics" Nov. 3, 1982.
It is, therefore, difficult to prepare against nested interrupt, because a restricted number of register sets are employed. To combat this problem, it is necessary to use a very large number of register sets. Indeed this system includes a greater number of register sets, but only one register set is employed, in practice, at a time during the run of a program, thus lowering the register's availability efficiency.
In the case where, upon the occurrence of an interrupt, the register's and inner states, for example, need to be saved or restored to the original state, it is not possible to disregard an attendant increase in a whole access time in a conventional continuous access system and it is also not possible to flexibly prepare against nested interrupt in the conventional register bank switching system.